The present invention relates to a data transmitter-receiver for transmitting and receiving a digital data in two-way fashion through a communication channel such as a telephone channel. Particularly, the invention relates to an involved echo canceler having an efficient delay control.
Generally, in fast full-duplex communication of a digital data through an analog telephone channel, the conventional data transmitter-receiver is provided with a modulator/demodulator of an audio band and an echo canceler for removing an echo noise reflected back through the telephone channel. For example, the modulator/demodulator (modem) adopts a four-phase pulse modulation (PM) mode or an eight-phase differential pulse modulation mode. In such a mode, the modulator/demodulator generally carries out digital signal processing on a real time basis according to a value-sampling operation which uses a sample point as a variable, or according to a differential operation. In turn, the echo canceler deals with an echo noise containing a close-end echo component which is reflected by an own two-wire/four-wire conversion hybrid, and containing a far-end echo component which is reflected back from a remote or opposite two-wire/four-wire conversion hybrid. Particularly, with regard to signal processing of the far-end echo component, a delay operation is conducted by delaying a signal transmitted from the modem (hereinafter, referred to as a "forward signal") by a time interval which is needed for the forward signal to return as a corresponding echo noise through a communication channel. The delayed forward signal is used to remove the echo noise mixed with a received signal which the moderm receives through the communication channel (hereinafter, referred to as a "backward signal").
However, the conventional data transmitter-receiver applies the delay operation to a modulated form of the forward signal, thereby disadvantageously requiring a great capacity of a delay memory which is used for the delay operation. Particularly, in the case that a data transfer speed reaches up to 9600 bps, a vast capacity of the delay memory is required, thereby disadvantageously causing scale-up of the device size and increase of the power consumption.